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DS21Q348DK 3.3V E1/T1/J1 Line Interface Design Kit Daughter Card
BASIC OPERATION
Hardware Configuration
Using the DK101 Processor Board:
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Connect the daughter card to the DK101 processor board.
Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is
unused. Additionally, the TIM 5V supply headers are unused.)
All processor-board DIP switch settings should be in the ON position with the exception of the flash-
programming switch, which should be OFF.
From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation in options were used, click the Start button on the Windows toolbar and select
Programs ? ChipView ? ChipView.
Using the DK2000 Processor Board:
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Connect the daughter card to the DK2000 processor board.
Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected
to connector J2.
From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation in options were used, click the Start button on the Windows toolbar and select
Programs ? ChipView ? ChipView.
General:
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Upon power-up, the RCL LEDs are lit, and the INT LED is off.
After power-up, the RCL LEDs extinguish upon external loopback.
Due to the dual winding transformer, only the 120 W line build-out configuration setting is needed to cover 75 W
E1 and 120 W E1.
Quick Setup (Register View)
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The PC loads the program, offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View.
The program requests a definition file. Select DS21Q348DK02A0_CPLD.DEF.
The Register View Screen appears, showing the register names, acronyms, and values. Note the CPLD def file
contains a link such that the def file for the DS21Q348 is also loaded. Selection among the def files is
accomplished using the drop-down box on the right-hand side of the program window.
From the drop-down box select the DS21Q348 def file and configure register CCR3 of ports 1 through 4 with a
90h.
–
The device begins transmitting a pseudorandom bit sequence. Upon external loopback, the RCL LED
extinguishes, denoting that the device has found a carrier and has successfully decoded the
pseudorandom bit sequence. For more advanced configurations, please refer to the DS21Q348 data
sheet.
Miscellaneous:
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Clock frequencies are provided by a register-mapped CPLD, which is on the DS21Q348 daughter card.
The definition file for this CPLD is named DS21Q348DK02A0_CPLD.def . See CPLD Register Map definitions.
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